Table 131. UEINT Register
UEINT (1.D6h) – USB Endpoint Interrupt Register
7
6
5
4
3
2
1
0
-
EPINT6
EPINT5
EPINT4
EPINT3
EPINT2
EPINT1
EPINT0
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The value read from these bits is always 0. Do not set these bits.
Endpoint Interrupts Bits
Set by hardware when an interrupt is triggered by the UEINTX register and if the
corresponding endpoint interrupt enable bit is set.
6-0
EPINT6:0
Cleared by hardware when the interrupt source is served.
Reset Value = 0000 0000b.
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AT85C51SND3Bx
7632A–MP3–03/06