AT8xC51SND2C
DAC Register Tables
Table 92. DAC Register Address
Address
00h
Register
DAC_CTRL
DAC_LLIG
DAC_RLIG
DAC_LPMG
DAC_RPMG
DAC_LLOG
DAC_RLOG
DAC_OLC
DAC_MC
Name
Access
Reset state
00h
Dac Control
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
01h
Dac Left Line in Gain
Dac Right Line in Gain
Dac Left Master Playback Gain
Dac Right Master Playback Gain
Dac Left Line Out Gain
Dac Right Line Out Gain
Dac Output Level Control
Dac Mixer Control
05h
02h
05h
03h
08h
04h
08h
05h
00h
06h
00h
07h
22h
08h
09h
Dac Clock and Sampling Frequency
Control
09h
DAC_CSFC
Read/Write
00h
0Ah
0Ch
0Dh
10h
11h
DAC_MISC
DAC_PRECH
DAC_AUXG
DAC_RST
Dac Miscellaneous
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
00h
00h
05h
00h
00h
Dac Precharge Control
Dac Auxilary input gain Control
Dac Reset
PA_CRTL
Power Amplifier Control
DAC Gain
The DAC implements severals gain control: line-in (Table 93.), master playback (), line-
out (Table 96.).
Table 93. Line-in gain
LLIG 4:0
RLIG 4:0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
Gain (dB)
20
12
9
6
3
0
-3
-6
-9
-12
-15
-18
-21
85
4341D–MP3–04/05
ATMEL [ ATMEL ]
