AT8xC51SND2C
Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in
cascade (see Figure 29). The selected input increments TL0 register. Figure 30 gives
the overflow period calculation formula when in timer mode.
Figure 29. Timer/Counter x (x = 0 or 1) in Mode 1
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
Overflow
THx
(8 bits)
TLx
(8 bits)
TFx
TCON Reg
Tx
C/Tx#
TMOD Reg
INTx
GATEx
TMOD Reg
TRx
TCON Reg
Figure 30. Mode 1 Overflow Period Formula
6 ⋅ (65536 – (THx, TLx))
TFxPER
=
FTIMx
Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads
Reload)
from TH0 register (see Table 64). TL0 overflow sets TF0 flag in TCON register and
reloads TL0 with the contents of TH0, which is preset by software. When the interrupt
request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next
reload value may be changed at any time by writing it to TH0 register. Figure 32 gives
the autoreload period calculation formula when in timer mode.
Figure 31. Timer/Counter x (x = 0 or 1) in Mode 2
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
Overflow
TLx
(8 bits)
TFx
TCON reg
Tx
C/Tx#
TMOD reg
INTx
THx
(8 bits)
GATEx
TMOD reg
TRx
TCON reg
Figure 32. Mode 2 Autoreload Period Formula
6 ⋅ (256 – THx)
TFxPER
=
FTIMx
Mode 3 (2 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (see Figure 33). This mode is provided for applications requiring an additional 8-
bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-
ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a
Timer function (counting FTF1/6) and takes over use of the Timer 1 interrupt (TF1) and
run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode
53
4341D–MP3–04/05
ATMEL [ ATMEL ]
