Figure 26. Timer 0 and Timer 1 Clock Controller and Symbols
PER
CLOCK
PER
CLOCK
0
0
1
Timer 0 Clock
Timer 1 Clock
1
OSC
CLOCK
OSC
CLOCK
÷ 2
÷ 2
T0X2
CKCON.1
T1X2
CKCON.2
TIM0
TIM1
CLOCK
CLOCK
Timer 0 Clock Symbol
Timer 1 Clock Symbol
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation.
Figure 27 through Figure 33 show the logical configuration of each mode.
Timer 0 is controlled by the four lower bits of TMOD register (see Table 63) and bits 0, 1,
4 and 5 of TCON register (see Table 62). TMOD register selects the method of Timer
gating (GATE0), Timer or Counter operation (C/T0#) and mode of operation (M10 and
M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control
bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-
rupt request.
It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 reg-
ister) with a modulo 32 prescaler implemented with the lower five bits of TL0 register
(see Figure 27). The upper three bits of TL0 register are indeterminate and should be
ignored. Prescaler overflow increments TH0 register. Figure 28 gives the overflow
period calculation formula.
Figure 27. Timer/Counter x (x = 0 or 1) in Mode 0
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
TLx
(5 Bits)
THx
(8 Bits)
Overflow
TFx
TCON reg
Tx
C/Tx#
TMOD Reg
INTx
GATEx
TMOD Reg
TRx
TCON Reg
Figure 28. Mode 0 Overflow Period Formula
6 ⋅ (16384 – (THx, TLx))
TFxPER
=
FTIMx
52
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
