AT8xC51SND2C
Timers/Counters
The AT8xC51SND2C implement 2 general-purpose, 16-bit Timers/Counters. They are
identified as Timer 0 and Timer 1, and can be independently configured to operate in a
variety of modes as a Timer or as an event Counter. When operating as a Timer, the
Timer/Counter runs for a programmed length of time, then issues an interrupt request.
When operating as a Counter, the Timer/Counter counts negative transitions on an
external pin. After a preset number of counts, the Counter issues an interrupt request.
The various operating modes of each Timer/Counter are described in the following
sections.
Timer/Counter
Operations
For instance, a basic operation is Timer registers THx and TLx (x = 0, 1) connected in
cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see
Table 62) turns the Timer on by allowing the selected input to increment TLx. When TLx
overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in
TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer
registers can be accessed to obtain the current count or to enter preset values. They
can be read at any time but TRx bit must be cleared to preset their values, otherwise,
the behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the
divided-down peripheral clock or external pin Tx as the source for the counted signal.
TRx bit must be cleared when changing the mode of operation, otherwise the behavior
of the Timer/Counter is unpredictable.
For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral
clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock
periods). The Timer clock rate is FPER/6, i.e., FOSC/12 in standard mode or FOSC/6 in X2
mode.
For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on
the Tx external input pin. The external input is sampled every peripheral cycles. When
the sample is high in one cycle and low in the next one, the Counter is incremented.
Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,
the maximum count rate is FPER/12, i.e., FOSC/24 in standard mode or FOSC/12 in X2
mode. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be held for
at least one full peripheral cycle.
Timer Clock Controller
As shown in Figure 26, the Timer 0 (FT0) and Timer 1 (FT1) clocks are derived from
either the peripheral clock (FPER) or the oscillator clock (FOSC) depending on the T0X2
and T1X2 bits in CKCON register. These clocks are issued from the Clock Controller
block as detailed in Section “Clock Controller”, page 12. When T0X2 or T1X2 bit is set,
the Timer 0 or Timer 1 clock frequency is fixed and equal to the oscillator clock fre-
quency divided by 2. When cleared, the Timer clock frequency is equal to the oscillator
clock frequency divided by 2 in standard mode or to the oscillator clock frequency in X2
mode.
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4341D–MP3–04/05
ATMEL [ ATMEL ]
