AT8xC51SND2C
Table 51. Priority Levels
IPHxx
IPLxx
Priority Level
0
0
1
1
0
1
0
1
0 Lowest
1
2
3 Highest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by
another interrupt of lower or equal priority. Higher priority interrupts are serviced before
lower priority interrupts. The response to simultaneous occurrence of equal priority inter-
rupts is determined by an internal hardware polling sequence detailed in Table 52.
Thus, within each priority level there is a second priority structure determined by the
polling sequence. The interrupt control system is shown in Figure 19.
Table 52. Priority within Same Level
Interrupt Request Flag
Interrupt Address
Vectors
Cleared by Hardware
(H) or by Software (S)
Interrupt Name
INT0
Priority Number
0 (Highest Priority)
C:0003h
C:000Bh
C:0013h
C:001Bh
C:0023h
C:002Bh
C:0033h
C:003Bh
C:0043h
C:004Bh
C:0053h
C:005Bh
C:0063h
C:006Bh
C:0073h
INT0
Timer 0
1
Timer 0
INT1
2
INT1
Timer 1
3
Timer 1
Serial Port
MP3 Decoder
Audio Interface
MMC Interface
Two Wire Controller
SPI Controller
Reserved
4
Serial Port
MP3 Decoder
Audio Interface
MMC Interface
Two Wire Controller
SPI Controller
Reserved
5
6
7
8
9
10
Keyboard
11
Keyboard
Reserved
12
13
Reserved
USB
USB
Reserved
14 (Lowest Priority)
Reserved
37
4341D–MP3–04/05
ATMEL [ ATMEL ]
