AT8xC51SND2C
External Space
Memory Interface
The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (RD, WR, and ALE).
Figure 15 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 28
describes the external memory interface signals.
Figure 15. External Data Memory Interface Structure
RAM
AT8xC51SND2C
PERIPHERAL
A15:8
P2
ALE
P0
A15:8
AD7:0
Latch A7:0
A7:0
D7:0
RD
OE
WR
WR
Table 28. External Data Memory Interface Signals
Signal
Name
Alternate
Function
Type Description
Address Lines
Upper address lines for the external bus.
A15:8
O
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
AD7:0
ALE
I/O
O
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
-
Read
RD
O
O
P3.7
P3.6
Read signal output to external data memory.
Write
WR
Write signal output to external memory.
Page Access Mode
The AT8xC51SND2C implement a feature called Page Access that disables the output
of DPH on P2 when executing MOVX @DPTR instruction. Page Access is enable by
setting the DPHDIS bit in AUXR register.
Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In
this case, software modifies intensively EXTRAM bit to select access to ERAM or XRAM
and must save it if used in interrupt service routine. Page Access allows external access
above 00FFh address without generating DPH on P2. Thus ERAM is accessed using
MOVX @Ri or MOVX @DPTR with DPTR < 0100h, < 0200h, < 0400h or < 0800h
depending on the XRS1:0 bits value. Then XRAM is accessed using MOVX @DPTR
with DPTR ≥ 0800h regardless of XRS1:0 bits value while keeping P2 for general I/O
usage.
25
4341D–MP3–04/05
ATMEL [ ATMEL ]
