External Bus Cycles
This section describes the bus cycles the AT8xC51SND2C executes to read (see
Figure 16), and write data (see Figure 17) in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode, refer to the Section “X2 Feature”, page 12.
Slow peripherals can be accessed by stretching the read and write cycles. This is done
using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR
signals from 3 to 15 CPU clock periods.
For simplicity, Figure 16 and Figure 17 depict the bus cycle waveforms in idealized form
and do not provide precise timing information. For bus cycle timing parameters refer to
the Section “AC Characteristics”.
Figure 16. External Data Read Waveforms
CPU Clock
ALE
RD(1)
DPL or Ri
D7:0
P0
P2
DPH or P2(2),(3)
P2
Notes: 1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
Figure 17. External Data Write Waveforms
CPU Clock
ALE
WR(1)
DPL or Ri
D7:0
P0
P2
DPH or P2(2),(3)
P2
Notes: 1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
26
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
