AT8xC51SND2C
Registers
Table 22. AUXR1 Register
AUXR1 (S:A2h) – Auxiliary Register 1
7
-
6
-
5
4
-
3
2
0
1
-
0
ENBOOT
GF3
DPS
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
-
The value read from these bits are indeterminate. Do not set these bits.
Enable Boot Flash
Set this bit to map the boot Flash in the code space between at addresses F000h
to FFFFh.
5
ENBOOT1
Clear this bit to disable boot Flash.
Reserved
4
3
-
The value read from this bit is indeterminate. Do not set this bit.
General Flag
This bit is a general-purpose user flag.
GF3
Always Zero
2
1
0
0
-
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
Reserved for Data Pointer Extension.
Data Pointer Select Bit
Set to select second data pointer: DPTR1.
Clear to select first data pointer: DPTR0.
DPS
Reset Value = XXXX 00X0b
Note: 1. ENBOOT bit is only available in AT89C51SND2C product.
21
4341D–MP3–04/05
ATMEL [ ATMEL ]
