AT8xC51SND2C
Table 30. AUXR Register
AUXR (S:8Eh) – Auxiliary Control Register
7
-
6
5
4
3
2
1
0
EXT16
M0
DPHDIS
XRS1
XRS0
EXTRAM
AO
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from this bit is indeterminate. Do not set this bit.
External 16-bit Access Enable Bit
Set to enable 16-bit access mode during MOVX instructions.
Clear to disable 16-bit access mode and enable standard 8-bit access mode
during MOVX instructions.
EXT16
M0
External Memory Access Stretch Bit
Set to stretch RD or WR signals duration to 15 CPU clock periods.
Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
5
DPH Disable Bit
4
DPHDIS Set to disable DPH output on P2 when executing MOVX @DPTR instruction.
Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.
Expanded RAM Size Bits
XRS1:0
3 - 2
Refer to Table 27 for ERAM size description.
External RAM Enable Bit
Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR
EXTRAM instructions.
1
0
Clear to select the internal expanded RAM when executing MOVX @Ri or MOVX
@DPTR instructions.
ALE Output Enable Bit
AO
Set to output the ALE signal only during MOVX instructions.
Clear to output the ALE signal at a constant rate of FCPU/3.
Reset Value = X000 1101b
29
4341D–MP3–04/05
ATMEL [ ATMEL ]
