Table 192. External Data 8-bit Bus Cycle - Write AC Timings
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLWL ALE Low to WR Low
TWLWH WR Pulse Width
ns
ns
ns
TWHLH WR High to ALE High
TAVWL Address Valid to WR Low
TQVWH Data Valid to WR High
TWHQX Data Hold after WR High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
ns
ns
ns
Waveforms
Figure 154. External Data 8-bit Bus Cycle - Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
216
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
