Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 194. External IDE 16-bit Bus Cycle - Data Read AC Timings
V
DD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLRL ALE Low to RD Low
TRLRH RD Pulse Width
ns
ns
ns
TRHLH RD high to ALE High
TAVDV Address Valid to Valid Data In
TAVRL Address Valid to RD Low
TRLDV RD Low to Valid Data
TRLAZ RD Low to Address Float
TRHDX Data Hold After RD High
TRHDZ Instruction Float After RD High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
4.5·TCLCL-65 ns
9·TCLCL-65
4·TCLCL-30
2·TCLCL-30
ns
5·TCLCL-30
0
2.5·TCLCL-30 ns
0
ns
ns
ns
0
0
2·TCLCL-25
TCLCL-25
Table 195. External IDE 16-bit Bus Cycle - Data Write AC Timings
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLWL ALE Low to WR Low
TWLWH WR Pulse Width
ns
ns
ns
TWHLH WR High to ALE High
TAVWL Address Valid to WR Low
TQVWH Data Valid to WR High
TWHQX Data Hold after WR High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
ns
ns
ns
218
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
