Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 197. SPI Interface Master AC Timing
V
DD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Slave Mode
Min
Max
Unit
TCHCH
Clock Period
2
TPER
TPER
TPER
ns
TCHCX
Clock High Time
Clock Low Time
SS Low to Clock edge
0.8
0.8
100
40
TCLCX
TSLCH, TSLCL
TIVCL, TIVCH
TCLIX, TCHIX
TCLOV, TCHOV
TCLOX, TCHOX
TCLSH, TCHSH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
SS High after Clock Edge
SS Low to Output Data Valid
Output Data Hold after SS High
SS High to SS Low
ns
40
ns
40
ns
0
0
ns
ns
TSLOV
TSHOX
TSHSL
TILIH
50
50
ns
ns
(1)
Input Rise Time
2
µs
µs
ns
ns
TIHIL
Input Fall Time
2
TOLOH
TOHOL
Output Rise time
100
100
Output Fall Time
Master Mode
TCHCH
Clock Period
2
TPER
TPER
TPER
ns
TCHCX
Clock High Time
0.8
0.8
20
20
TCLCX
Clock Low Time
TIVCL, TIVCH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
TCLIX, TCHIX
TCLOV, TCHOV
TCLOX, TCHOX
ns
40
ns
0
ns
TILIH
TIHIL
2
2
µs
Input Data Fall Time
µs
TOLOH
TOHOL
Note:
Output Data Rise time
50
50
ns
Output Data Fall Time
ns
1. Value of this parameter depends on software.
220
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
