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83C51SND2C-JL 参数 Datasheet PDF下载

83C51SND2C-JL图片预览
型号: 83C51SND2C-JL
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片闪存微控制器与MP3解码器,支持完整的音频接口 [Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface]
分类和应用: 解码器闪存微控制器
文件页数/大小: 235 页 / 2877 K
品牌: ATMEL [ ATMEL ]
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Data Line Controller  
The data line controller is based on a 16-Byte FIFO used both by the data transmitter  
channel and by the data receiver channel.  
Figure 95. Data Line Controller Block Diagram  
MMINT.0  
MMINT.2  
MMSTA.3  
MMSTA.4  
F1EI  
F1FI  
DATFS CRC16S  
CRC16 and Format  
Checker  
Data Converter  
Serial -> //  
8-Byte  
TX Pointer  
FIFO 1  
MCBI  
MMINT.1  
CBUSY  
MMSTA.5  
MDAT  
DTPTR  
MMCON0.6  
16-Byte FIFO  
MMDAT  
Data Converter  
// -> Serial  
CRC16  
Generator  
RX Pointer  
DRPTR  
MMCON0.7  
8-Byte  
FIFO 2  
MMINT.4  
DATA Line  
Finished State Machine  
EOFI  
DFMT  
MBLOCK DATEN DATDIR BLEN3:0  
MMCON0.2 MMCON0.3 MMCON1.2 MMCON1.3 MMCON1.7:4  
F2EI  
MMINT.1  
F2FI  
MMINT.3  
FIFO Implementation  
The 16-Byte FIFO is based on a dual 8-Byte FIFOs managed using 2 pointers and four  
flags indicating the status full and empty of each FIFO.  
Pointers are not accessible to user but can be reset at any time by setting and clearing  
DRPTR and DTPTR bits in MMCON0 register. Resetting the pointers is equivalent to  
abort the writing or reading of data.  
F1EI and F2EI flags in MMINT register signal when set that respectively FIFO1 and  
FIFO2 are empty. F1FI and F2FI flags in MMINT register signal when set that respec-  
tively FIFO1 and FIFO2 are full. These flags may generate an MMC interrupt request as  
detailed in Section “Interrupt”.  
Data Configuration  
Before sending or receiving any data, the data line controller must be configured accord-  
ing to the type of the data transfer considered. This is achieved using the Data Format  
bit: DFMT in MMCON0 register. Clearing DFMT bit enables the data stream format  
while setting DFMT bit enables the data block format. In data block format, user must  
also configure the single or multi-block mode by clearing or setting the MBLOCK bit in  
MMCON0 register and the block length using BLEN3:0 bits in MMCON1 according to  
Table 144. Figure 96 summarizes the data modes configuration flows.  
Table 144. Block Length Programming  
BLEN3:0  
BLEN = 0000 to 1011  
> 1011  
Block Length (Byte)  
Length = 2BLEN: 1 to 2048  
Reserved: do not program BLEN3:0 > 1011  
144  
AT8xC51SND2C  
4341D–MP3–04/05  
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