Command Line
Controller
As shown in Figure 93, the command line controller is divided in 2 channels: the com-
mand transmitter channel that handles the command transmission to the card through
the MCMD line and the command receiver channel that handles the response reception
from the card through the MCMD line. These channels are detailed in the following
sections.
Figure 93. Command Line Controller Block Diagram
Data Converter
// -> Serial
CRC7
Generator
TX Pointer
5-Byte FIFO
MMCMD
Write
CTPTR
MMCON0.4
TX COMMAND Line
Finished State Machine
MMINT.5
EOCI
CFLCK
MMSTA.0
CMDEN
MMCON1.0
MCMD
Command Transmitter
MMSTA.2
MMSTA.1
CRC7S RESPFS
Data Converter
Serial -> //
CRC7 and Format
Checker
RX Pointer
17 - Byte FIFO
MMCMD
Read
CRPTR
MMCON0.5
RX COMMAND Line
Finished State Machine
MMINT.6
EORI
RESPEN RFMT CRCDIS
MMCON1.1 MMCON0.1 MMCON0.0
Command Receiver
Command Transmitter
For sending a command to the card, user must load the command index (1 Byte) and
argument (4 Bytes) in the command transmit FIFO using the MMCMD register. Before
starting transmission by setting and clearing the CMDEN bit in MMCON1 register, user
must first configure:
•
•
•
RESPEN bit in MMCON1 register to indicate whether a response is expected or not.
RFMT bit in MMCON0 register to indicate the response size expected.
CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the
response will be computed or not. In order to avoid CRC error, CRCDIS may be set
for response that do not include CRC7.
Figure 94 summarizes the command transmission flow.
As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicat-
ing that write to the FIFO is locked. This mechanism is implemented to avoid command
overrun.
The end of the command transmission is signalled to you by the EOCI flag in MMINT
register becoming set. This flag may generate an MMC interrupt request as detailed in
Section "Interrupt", page 150. The end of the command transmission also resets the
CFLCK flag.
142
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
