Universal Serial Bus The AT8xC51SND2C implements a USB device controller supporting full speed data
transfer. In addition to the default control endpoint 0, it provides 2 other endpoints, which
can be configured in control, bulk, interrupt or isochronous modes:
•
•
Endpoint 0: 32-Byte FIFO, default control endpoint
Endpoint 1, 2: 64-Byte Ping-pong FIFO,
This allows the firmware to be developed conforming to most USB device classes, for
example:
•
•
•
USB Mass Storage Class Bulk-only Transport, Revision 1.0 - September 31, 1999
USB Human Interface Device Class, Version 1.1 - April 7, 1999
USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999
USB Mass Storage Class
Bulk-Only Transport
Within the Bulk-only framework, the Control endpoint is only used to transport class-
specific and standard USB requests for device set-up and configuration. One Bulk-out
endpoint is used to transport commands and data from the host to the device. One Bulk
in endpoint is used to transport status and data from the device to the host.
The following AT8xC51SND2C configuration adheres to those requirements:
•
•
•
Endpoint 0: 32 Bytes, Control In-Out
Endpoint 1: 64 Bytes, Bulk-in
Endpoint 2: 64 Bytes, Bulk-out
USB Device Firmware
Upgrade (DFU)
The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip
Flash memory of the AT89C51SND2C. This allows installing product enhancements
and patches to devices that are already in the field. 2 different configurations and
descriptor sets are used to support DFU functions. The Run-Time configuration co-exist
with the usual functions of the device, which is USB Mass Storage for AT89C51SND2C.
It is used to initiate DFU from the normal operating mode. The DFU configuration is
used to perform the firmware update after device re-configuration and USB reset. It
excludes any other function. Only the default control pipe (endpoint 0) is used to support
DFU services in both configurations.
The only possible value for the MaxPacketSize in the DFU configuration is 32 Bytes,
which is the size of the FIFO implemented for endpoint 0.
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AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
