Data Bus (D0 through
D31)
This 32-bit, bi-directional, three-state bus serves as the general-purpose data path
between the TS68020/TS68030 and the TS68882. Regardless of whether the TS68882
is operated as a co-processor or a peripheral processor, all inter-processor transfers of
instruction information, operand data, status information, and requests for service occur
as standard TS68000 bus cycles.
The TS68882 will operate over an 8-, 16-, or 32-bit system data bus. Depending upon
the system data bus configuration, both the A0 and SIZE pins are configured specifically
for the applicable bus configuration. (Refer to ADDRESS BUS (A0 through A4) and
SIZE (SIZE for further details).
Size (SIZE)
This active-low input signal is used in conjunction with the A0 pin to configure the
TS68882 for operation over an 8-, 16-, or 32-bit system data bus. When the TS68882 is
configured to operate over a 16-or 32-bit system data bus, both the SIZE and A0 pins
are strapped high and/or low as listed in Table 11.
Address Strobe (AS)
Chip Select (CS)
This active-low input signal indicates that there is a valid address on the address bus,
and both the chip select (CS) and read/write (R/W signal lines are valid).
This active-low input signal enables the main processor access to the TS68882 co-pro-
cessor interface registers. When operating the TS68882 as a peripheral processor, the
chip select decode is system dependent (i.e., like the chip select on any peripheral). The
CS signal must be valid (either asserted or negated) when AS is asserted. Refer to
CHIP SELECT TIMING for further discussion of timing restrictions for this signal.
Read/Write (R/W)
Data Strobe (DS)
This input signal indicates the direction of a bus transaction (read/write) by the main pro-
cessor. A logic high (1) indicates a read from the TS68882, and a logic low (0) indicates
a write to the TS68882. The R/W signal must be valid when AS is asserted.
This active-low input signal indicates that there is valid data on the data bus during a
write bus cycle.
Data Transfer and Size
Acknowledge (DSACK0,
DSACK1)
These active-low, three-state output signals indicate the completion of a bus cycle to the
main processor. The TS68882 asserts both the DSACK0, and DSACK1 signals upon
assertion of CS.
If the bus cycle is a main processor read, the TS68882 asserts DSACK0 and DSACK1
signals to indicate that the information on the data bus is valid. (Both DSACK signals
may be asserted in advance of the valid data being placed on the bus). If the bus cycle
is a main processor write to the TS68882, DSACK0 and DSACK1 are used to acknowl-
edge acceptance of the data by the TS68882.
The TS68882 also uses DSACK0 and DSACK1 signals to dynamically indicate to the
TS68020/TS68030 the “port” size (system data bus width) on a cycle-by-cycle basis.
Depending upon which of the two DSACK pins are asserted in a given bus cycle, the
TS68020/TS68030 assumes data has been transferred to/from an 8-, 16-, or 32-bit wide
data port. Table 12 lists the DSACK assertions that are used by the TS68882 for the
various bus cycles over the various bus cycles over the various system data bus
configurations.
32
TS68882
2119A–HIREL–04/02
ATMEL [ ATMEL ]
