TS68882
FADD
Add
FSGLDIV
FSGLMUL
FSUB
Single Precision Divide
Single Precision Multiply
Subtract
Branch, Set, and Trap-on The floating-point branch, set, and trap-on condition instructions implemented by the
TS68882 are similar to the equivalent integer instructions of the TS68000 Family pro-
Condition
cessors, except that more conditions exist due to the special values in IEEE floating-
point arithmetic. When a conditional instruction is executed, the TS68882 performs the
necessary condition checking and tells the MPU whether the condition is true or false;
the MPU then takes the appropriate action. Since the TS68882 and TS68020/TS68030
are closely coupled, the floating-point branch operations executed by the pair are very
fast.
The TS68882 conditional operations are:
FBcc
FDBcc
FScc
Branch
Decrement and Branch
Set Byte According to Condition
Trap-on Condition (with an Optional
Parameter)
FTRAPcc
where:
cc is one of the 32 floating-point conditional test specifiers as shown in Table 9.
rs
Table 9. Floating-point Conditional Test Specifiers
Mnemonic Definition
Note: The following conditional tests do not set the BSUN bit in the status register exception byte under any circumstances.
F
False
EQ
Equal
OGT
OGE
OLT
OLE
OGL
OR
Ordered Greater Than
Ordered Greater Than or Equal
Ordered Less Than
Ordered Less Than or Equal
Ordered Greater or Less Than
Ordered
UN
Unordered
UEQ
UGT
UGE
ULT
ULE
NE
Unordered or Equal
Unordered or Greater Than
Unordered or Greater or Equal
Unordered or Less Than
Unordered or Less or Equal
Not Equal
29
2119A–HIREL–04/02
ATMEL [ ATMEL ]
