Table 9. Floating-point Conditional Test Specifiers (Continued)
Mnemonic
Definition
T
True
Note: The following conditional tests set the BSUN bit in the status register exception byte if the NAN condition code bit is set when a
conditional instruction is executed.
SF
Signaling False
SEQ
GT
Signaling Equal
Greater Than
GE
Greater Than or Equal
Less Than
LT
LE
Less Than or Equal
Greater or Less Than
Greater Less or Equal
Not (Greater, Less or Equal)
Not (Greater or Less)
Not (Less or Equal)
Not (Less Than)
GL
GLE
NGLE
NGL
NLE
NLT
NGE
NGT
SNE
ST
Not (Greater or Equal)
Not (Greater Than)
Signaling Not Equal
Signaling True
Miscellaneous
Instructions
Miscellaneous instructions include moves to and from the status, control, and instruction
address registers and a no operation function that can be used to “flush” exceptions.
Also included are the virtual memory/machine FSAVE and FRESTORE instructions that
save and restore the internal state of the TS68882.
FMOVE
FMOVE
FNOP
(ea),FPcr
Move to Control Register(s)
Move from Control Register(s)
No Operation
FPcr,(ea)
FSAVE
(ea)
(ea)
Virtual Machine State Save
Virtual Machine State Restore
FRESTORE
Addressing Modes
The TS68882 does not perform address calculations. This satisfies the criterion that a
TS68000 Family co-processor must not depend on certain features or capabilities that
may or may not be implemented by a given main processor. Thus, when the TS68882
instructs the TS68020/TS68030 to transfer an operand via the co-processor interface,
the MPU performs the addressing mode calculations requested in the instruction. In this
case, the instruction is encoded specifically for the TS68020/TS68030, and the execu-
tion of the TS68882 is not dependent on that encoding, but only on the value of the
command word written to the TS68882 by the main processor.
30
TS68882
2119A–HIREL–04/02
ATMEL [ ATMEL ]
