TS68882
Figure 15. Accrued Exception Byte
Figure 16. Typical Co-processor Configuration
Bus Interface Unit
All communications between the TS68020/TS68030 and the TS68882 occur via stan-
dard TS68000 Family bus transfers. The TS68882 is designed to operate on 8-, 16-, or
32-bit data buses.
The TS68882 contains a number of co-processor interface registers (CIRs) which are
addresses in the same manner as memory by the main processor. The TS68000 Family
co-processor interface is implemented via a protocol of reading and writing to these reg-
isters by the main processor. The TS68020 and TS68030 implements this general-
purpose co-processor interface protocol in hardware and microcode.
When the TS68020/TS68030 detects a typical TS68882 instruction, the MPU writes the
instruction to the memory-mapped command CIR, and reads the response CIR. In this
response, the BIU encodes requests for any additional action required of the MPU on
behalf of the TS68882. For example, the response may request that the MPU fetch an
operand from the evaluated effective address and transfer the operand to the operated
CIR. Once the MPU fulfills the co-processor request(s), it is free to fetch and execute
subsequent instructions.
21
2119A–HIREL–04/02
ATMEL [ ATMEL ]
