Functional
Description
The Co-processor
Concept
The TS68882 functions as a co-processor in systems where the TS68020 or TS68030 is
the main processor via the TS68000 co-processor interface. It functions as a peripheral
processor in systems where the main processor is the TS68000, TS68010.
The TS68882 utilizes the TS68000 Family co-processor interface to provide extension
of the TS68020 /TS68030 registers and instruction set in a manner which is transparent
to the programmer. The programmer perceives the MPU/FPCP execution model as if
both devices are implemented on one chip.
A fundamental goal of the TS68000 Family co-processor interface is to provide the pro-
grammer with an execution model based upon sequential instruction execution by the
TS68020/TS68030 and the TS68882. For optimum performance, however, the co-pro-
cessor interface allows concurrent operations in the TS68882 with respect to the
TS68020/TS68030 whenever possible. In order to simplify the programmer’s model, the
co-processor interface is designed to emulate, as closely as possible, non-concurrent
operation between the TS68020/TS68030 and the TS68882.
The TS68882 is s non-DMA type co-processor which uses a subset of the general-pur-
pose co-processor interface supported by the TS68020/TS68030. Features of the
interface implemented in the TS68882 are as follows:
•
The main processor(s) and TS68882 communicate via standard TS68000 bus
cycles
•
The main processor(s) and TS68882 communications are not dependent upon the
instruction sets or internal details of the individual devices (i.e., instruction pipes or
caches, addressing modes)
•
•
The main processor(s) and TS68882 may operate at different clock speeds
TS68882 instructions utilize all addressing modes provided by the main processor;
all effective addresses are calculated by the main processor at the request of the co-
processor
•
All data transfers are performed by the main processor at the request of the
TS68882; thus memory management, bus errors, address errors, and bus
arbitration function as if the TS68882 instructions are executed by the main
processor
•
•
Overlapped (concurrent) instruction execution enhances throughput while
maintaining the programmer’s model of sequential instruction execution
Co-processor detection of exceptions which require a trap to be taken are serviced
by the main processor at the request of the TS68882 thus exception processing
functions as if the TS68882 instructions were executed by the main processor
•
•
•
Support of virtual memory/virtual machine systems is provided via the FSAVE and
FRESTORE instructions
Up to eight co-processors may reside in a system simultaneously: multiple co-
processors of the same type are also allowed
Systems may use software emulation of the TS68882 without reassembling or
relinking user software
18
TS68882
2119A–HIREL–04/02
ATMEL [ ATMEL ]
