TS68882
The TS68882 programming model is shown in Figure 10 through 15, and consists of the
following:
•
Eight 80-bit floating-point data registers (FP0-FP7). These registers are analogous
to the integer data registers (D0-D7) and are completely general-purpose (i.e., any
instruction may use any register)
•
•
•
A 32-bit control register that contains enable bits for each class of exceptions trap,
and mode bits to set the user-selectable rounding and precision modes
A 32-bit status register that contains floating-point condition codes, quotient bits,
and exception status information
A 32-bit instruction address register that contains the main processor memory
address of the last floating-point instruction that was executed. This address is used
in exception handling to locate the instruction that caused the exception
The connection between the TS68020/TS68030 and the TS68882 is a simple extension
of the TS68000 bus interface. The TS68882 is connected as a co-processor to the
TS68020/TS68030, and the selection of the TS68882 is based upon a chip select (CS),
which is decoded from the TS68020/TS68030 function codes and address bus. Figure
16 illustrates the TS68882/TS68020 or TS68030 configuration.
Figure 10. TS68882 Programming Model
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2119A–HIREL–04/02
ATMEL [ ATMEL ]
