TS68882
Figure 9. Synchronous Read Cycle Timing Diagram
Note:
START is actually a logical condition, but is shown as an active signal for clarity. The logical equation for this signal is: START =
CS + AS + (R/W · DS).
Additional Information
Additional information shall not be for any inspection purposes.
Capacitance (Not for Inspection Purposes)
Symbol Parameter
Test Conditions
Vin = 0 Tamb = 25°C
f = 1 MHz
Min
Max
Unit
Cin
Input Capacitance
20
pF
17
2119A–HIREL–04/02