A key concern in a co-processor interface that allows concurrent instruction execution is
synchronization during main processor and co-processor communication. If a subse-
quent instruction is written to the TS68882 before the CCU has passed the operands for
the previous instructions to the ECU, the response instructs the TS68020/TS68030 to
wait. Thus, the choice of concurrent or nonconcurrent instruction execution is deter-
mined on an instruction-by-instruction basis by the co-processor.
The only difference between a co-processor bus transfer and any other bus transfer is
that the TS68020/TS68030 issues a function code to indicate the CPU address space
during the cycle (the function codes are generated by the TS68000 Family processors to
identify eight separate address spaces). Thus, the memory-mapped co-processor inter-
face registers do not infringe upon instruction or data address spaces. The
TS68020/TS68030 places a co-processor ID field from the co-processor instruction onto
three of the upper address lines during co-processor accesses. This ID, along with the
CPU address space function code, is decoded to select one of eight co-processors in
the system.
Since the co-processor interface protocol is based solely on bus transfers, the protocol
is easily emulated by software when the TS68882 is used as a peripheral with any pro-
cessor capable of memory-mapped I/O over on TS68000 style bus. When used as a
peripheral processor with the 8-bit TS68008 or the 16-bit TS68000, or TS68010, all
TS68882 instructions are trapped by the main processor to an exception handler at exe-
cution time. Thus, the software emulation of the processor interface protocol can be
totally transparent to the user. The system can be quickly upgraded by replacing the
main processor with a TS68020/TS68030 without changes to the user software.
Since the bus is asynchronous, the TS68882 need not run at the same clock speed as
the main processor. Total system performance may therefore be customized. For exam-
ple, a system requiring very fast floating-point arithmetic with relatively slow integer
arithmetic can be designed with an inexpensive main processor and a fast TS68882.
Co-processor Interface
The TS68000 Family co-processor interface is an integral part of the TS68882 and
TS68020/TS68030 designs, with the interface tasks shared between the two. The inter-
face is fully compatible with all present and future TS68000 Family products. Tasks are
partitioned such that the TS68020/TS68030 does not have to decode co-processor
instructions and, the TS68882 does not have to duplicate main processor functions such
as effective address evaluation.
This partitioning provides an orthogonal extension of the instruction set by permitting
TS68882 instructions to utilize all TS68020/TS68030 addressing modes and to gener-
ate execution time exception traps. Thus, from the programmer’s view, the CPU and co-
processor appear to be integrated onto a single chip. While the execution of the majority
of TS68882 instructions may be overlapped with the execution of TS68020/TS68030
instructions, concurrency is completely transparent to the programmer. The
TS68020/TS68030 single-step and program flow (trace) modes are fully supported by
the TS68882 and the TS68000 Family co-processorco-processor interface.
While the TS68000 Family co-processor interface permits co-processors to be bus mas-
ters, the TS68882 is never a bus master. The TS68882 requests that the
TS68020/TS68030 fetch all operands and store all results. In this manner, the
TS68020/TS68030 32-bit data bus provides high speed transfer of floating-point oper-
ands and results while simplifying the design of the TS68882.
22
TS68882
2119A–HIREL–04/02
ATMEL [ ATMEL ]
