Signal Pins Description
Pin Number
9
8
11
13
10
23
22
16
5, 4, 3, 2, 44, 43,
42, 41
38, 37, 36, 35, 33,
32, 31, 30
25
27
19
14
15
26
20
Signal
Name
Mode
Cs
Wr
Rd
ALE
Xtalin
Xtalout
Reset
addr<7:0>
Data<7:0>
Int
Can_tx
Can_rx
sena
test
hatrig
hasync
Type
I - CMOS
I - CMOS
I - CMOS
I - CMOS
I - CMOS
I - CMOS
IO - CMOS
I - CMOS
I - CMOS
IO - CMOS
O - CMOS
O - CMOS
I - CMOS
I - CMOS
I - CMOS
O - CMOS
O - CMOS
AH
AH
AH
AH
AL
AL
AH
AL
AL
AH
Note
Description
Interface operational mode
Chip select signal
Write signal
Read signal
Address latch enable
Input to internal oscillators or clock
input from external oscillator
Output from internal oscillator
reset signal
Input address(mode1) or output
address(mode 0)
Address data bus
interrupt request
tx signal
rx signal
scan enable
input signal to increase testability
Output signal to trigger the message
matching
Output synchronization signal
Note:
Abbreviations: O = output, I = input, IO = bi-directional I/O, AL = Active Low, AH = Active
High.
2
AT7908E
4268D–AERO–11/09
ATMEL [ ATMEL CORPORATION ]
