BPR0
BPR1
System clock frequency
0
0
1
1
0
1
0
1
fosc
fosc/2
fosc/4
fosc/8
SETUP_1:
TXDLC<3:0>: length of the transmitted message.
TMRMR: Active High, establishes if the transmitted message is a remote frame (if
TXRM=0).
TXEM: active high, it establishes if the transmitted message is an extended frame.
TXRM: Active high, it establishes if the controller answers to the remote frame request
(if TMRMR=0).
Disabled: active high, by setting this bit, the CAN controller is disabled and discon-
nected from the bus. This condition could be used to set the other registers safely. The
error counter values, when this bit is active, will be frozen at the last value.
SETUP_2:
SETUP_3 :
PS1_3 … PS1_0: these 4 bits are the phase segment length 1 (acceptable value 1:15).
The default value of this register (value after reset) is 9 decimal.
PS2_3 … PS2_0: these 4 bits are the phase segment length 2 (acceptable value 1:8).
The default value of this register (value after reset) is 5 decimal.
RSJ_2 … RSJ_0: 3 bits for the re-synchronization jump (correct value 1:4). The default
value is 2.
Txreq: when this bit is set high, the AT7908E sends on the CAN bus the message con-
tained in the TX buffer. This bit must be written from the MCU to start the transmission.
AbortTx: this bit must be set to inform the interface that the transmission request has to
be aborted. The error counter values are not reset when this bit is set.
IntClr: this bit resets the INT signal of the device and clears the SyncTx and SyncRx
bits of the STATUS register.
Reset: active high, this signal must be set to reset the CAN controller. The error condi-
tion is cleared and also the counter values.
RxClr: active high, this bit is set to clear all RXOKn and RXOVRn bits on the status reg-
ister of the receiver message buffers (STATUS_RX).
SETUP_RX Register
RxClr3: active high, this bit is set to clear the RXOK3 and RXOVR3 bits on the status
register of the receiver message buffer (STATUS_RX). This bit must be set after the
read out operation of the received message otherwise, at the next reception on the
same RX message buffer, an overrun condition is raised.
RxClr2: active high, this bit is set to clear the RXOK2 and RXOVR2 bits on the status
register of the receiver message buffers. This bit must be set after the read out opera-
tion of the received message otherwise, at the next reception on the same RX message
buffer, an overrun condition is raised.
12
AT7908E
4268D–AERO–11/09
ATMEL [ ATMEL ]
