will be shortened (TSEG2 is shortened of RSJ value). The resynchronization mecha-
nism is shown in fig. 3 and fig. 4.
Figure 3. Lengthening a Bit Period
Input signal
SYNC
Timing Segment 1
RSJ Timing
Sample point
Figure 4. Shortening a Bit Period
Input signal
SYNC
Timing Segment 1
Timing Segment 2
RSJ
Sample point
Tseg2 will be shortened
of RSJ value
The Bit rate of the message on the bus will be:
fosc/(BPR(baud rate prescaler)x(TSEG1 +TSEG2+1)) =
= fosc /(BPR(baud rate prescaler) x( PS1 +PS2 +2))
The TSEG1 and TSEG2 lengths must be programmed to respect these conditions:
TSEG1 ³ TSEG2 => PS1 +1 ³ PS2
TSEG2 ³ RSJ => PS2 ³ RSJ
16
AT7908E
4268D–AERO–11/09
ATMEL [ ATMEL ]
