ATF2500C Family
Output Logic, Registered
(1)
S2 = 0
S1
0
1
1
S0
0
0
1
Terms in
D/T1
8
12
8
D/T2
4
4
(1)
4
Output Configuration
Registered (Q1); Q2 FB
Registered (Q1); Q2 FB
Registered (Q1); D/T2 FB
S3
0
1
Output
Configuration
Active Low
Active High
S6
0
1
Q1 CLOCK
CK1
CK1 • PIN1
S4
0
1
Register 1 Type
D
T
S7
0
1
Q2 CLOCK
CK2
CK2 • PIN1
S5
0
1
Register 2 Type
D
T
Output Logic, Combinatiorial
(1)
S5
X
X
X
1
0
S2 = 1
S1
0
0
1
1
1
S0
0
1
0
1
1
Terms in
D/T1
4
(1)
4
4
(1)
4
(1)
4
D/T2
4
4
4
(1)
4
4
Output Configuration
Combinatorial (8 Terms);
Q2 FB
Combinatorial (4 Terms);
Q2 FB
Combinatorial (12 Terms);
Q2 FB
Combinatorial (8 Terms);
D/T2 FB
Combinatorial (4 Terms);
D/T2 FB
Note:
1. These four terms are shared with D/T1.
Clock Option
Note:
1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
7
0777G–12/01
ATMEL [ ATMEL CORPORATION ]
