ATF2500C Family
Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises
in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3. The clock pin, and any signals from which clock terms are derived, must remain stable
during tPR
.
Parameter
tPR
Description
Typ
600
3.8
Max
1000
4.5
Units
ns
Power-up Reset Time
VRST
Power-up Reset Voltage
V
Level Forced on
Odd I/O Pin during
PRELOAD Cycle
Q Select Pin
State
Even/Odd
Select
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
VIH/VIL
VIH/VIL
VIH/VIL
VIH/VIL
Low
High
Low
High
Low
High/Low
X
X
X
Low
X
X
X
High/Low
X
High/Low
X
X
X
High
High
X
X
High/Low
3
0777G–12/01
ATMEL [ ATMEL ]
