Table 5. External Data Memory Characteristics (ns)
30 MHz
Symbol
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
Parameter
min
max
RD Pulse Width
180
180
WR Pulse Width
RD to Valid Data In
135
Data Hold After RD
0
Data Float After RD
ALE to Valid Data In
Address to Valid Data In
ALE to WR or RD
70
235
260
115
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
TWHLH
90
115
20
Address to WR or RD
Data Valid to WR Transition
Data set-up to WR High
Data Hold After WR
RD Low to Address Float
RD or WR High to ALE high
215
20
0
20
40
Figure 8. External Data Memory Write Cycle
TWHLH
TLLDV
ALE
PSEN
RD
TLLWL
TRLRH
TRLDV
TRHDZ
TAVDV
TLLAX
TRHDX
DATA IN
PORT 0
PORT 2
A0-A7
TRLAZ
TAVWL
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
14
80C32E
Rev. K – 21-Aug-01
ATMEL [ ATMEL ]
