Table 7. External Clock Drive Characteristics (XTAL1)
Symbol
TCLCL
Parameter
Oscillator Period
Min
33.33
5
Max
Units
ns
TCHCX
TCLCX
TCLCH
TCHCL
High Time
Low Time
Rise Time
Fall Time
ns
5
ns
5
5
ns
ns
Figure 11. External Clock Drive Waveforms
VCC-0.5 V
0.7VCC
0.2VCC-0.1 V
TCHCX
0.45 V
TCHCL
TCLCH
TCLCX
TCLCL
Figure 12. AC Testing Input/Output Waveforms
VCC-0.5 V
0.2VCC+0.9
0.2VCC-0.1
INPUT/OUTPUT
0.45 V
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
Figure 13. Float Waveforms
FLOAT
VOH-0.1 V
VOL+0.1 V
VLOAD
VLOAD+0.1 V
VLOAD-0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH ≥ ± 20mA.
16
80C32E
Rev. K – 21-Aug-01
ATMEL [ ATMEL ]
