DC Parameters
TA = -55°C to +125°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 30 MHz.
Table 3. DC Parameters in Standard Voltage
Symbol
Parameter
Input Low Voltage
Min.
Max
Unit
Test Conditions
VIL
-0.5
0.2 VCC - 0.1
V
0.2 VCC
1.4
+
VIH
Input High Voltage except XTAL1, RST
VCC + 0.5
V
VIH1
VOL
Input High Voltage, XTAL1, RST
0.7 VCC
VCC + 0.5
0.45
V
V
V
Output Low Voltage, ports 1, 2, 3 (5)
Output Low Voltage, port 0, ALE, PSEN
IOL = 1.6 mA(4)
IOL = 3.2 mA(4)
(5)
VOL1
0.45
2.4
V
V
V
IOH = -60 µA
IOH = -25 µA
VOH
Output High Voltage, ports 1, 2, 3
0.75 VCC
0.9 VCC
I
OH = -10 µA
2.4
V
V
V
I
I
I
OH = -400 µA
OH = -150 µA
OH = -40 µA
Output High Voltage, port 0, ALE, PSEN
VOH1
0.75 VCC
0.9 VCC
RRST
IIL
RST Pull-down Resistor
50
200
-75
kΩ
Logical 0 Input Current ports 1, 2 and 3
Input Leakage Current
µA Vin = 0.45 V
ILI
±10
µA 0.45 V < Vin < VCC
Logical 1 to 0 Transition Current, ports 1,
2, 3
ITL
-750
µA Vin = 2.0 V
Fc = 1 MHz
pF
CIO
IPD
Capacitance of I/O Buffer
Power Down Current (3)
10
75
TA = 25°C
µA 2.0 V < VCC < 5.5 V
Power Supply Current (1)(2)(6)
Freq= 1 MHz Icc Op
Freq= 1 MHz Icc Idle
Freq= 6 MHz Icc Op
Freq= 6 MHz Icc Idle
Freq >12 MHz Icc Op
Freq >12 MHz Icc Idle
V
CC = 5.5 V
1.8
mA
mA
mA
mA
mA
mA
1
10
ICC
4
1.25 F + 5
0.36 F + 2.7
F in MHz
Notes: 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with
TCLCH, TCHCL = 5 ns (see Figure 6.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if
a crystal oscillator used.
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH
,
T
CHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST
= VSS (see Figure 4.).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 =
CC; XTAL2 NC.; RST = VSS (see Figure 5.).
V
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be super-
imposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus
capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the
10
80C32E
Rev. K – 21-Aug-01
ATMEL [ ATMEL ]
