APW7098
Application Information
Output Voltage Setting
FLC
The output voltage is adjustable from 0.6V to 2.5V
with a resistor-divider connected with FB, AGND, and
converter’s output. Using 1% or better resistors for the
resistor-divider is recommended. The output voltage
is determined by:
-40dB/dec
æ
ç
è
ö
RTOP
RGND
FESR
VOUT = 0.6 ´ 1+
ç
÷
÷
ø
Where 0.6 is the reference voltage, RTOP is the resistor
connected from converter’s output to FB, and RGND is the
resistor connected from FB to the the AGND. Suggested
RGND is in the range from 1K to 20kW. To prevent stray
pickup, locate resistors RTOP and RGND close to the
APW7098.
-20dB/dec
Frequency(Hz)
Figure 6. Frequency Resopnse of the LC filters
PWM Compensation
The PWM modulator is shown in figure 7. The input is the
output of the error amplifier and the output is the PHASE
node. The transfer function of the PWM modulator is given
by :
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB, and VOUT
should be added. The compensation network is shown
in Figure 8. The output LC filters consists of the
output inductors and output capacitors. For two-phase
convertor, when assuming VIN1=VIN2=VIN, L1=L2=L, the
transfer function of the LC filter is given by:
V
IN
GAINPWM
=
DVOSC
VIN
Driver
OSC
PWM
Comparator
1+ s´ ESR´ COUT
GAINLC
=
PHASE
1
s2 ´ L´ COUT + s´ ESR´ COUT +1
DVOSC
2
Output of Error
Amplifier
The poles and zero of this transfer functions are:
1
Driver
F
=
LC
1
2
2´ p ´
L´ COUT
Figure 7. The PWM Modulator
1
The compensation network is shown in figure 8. It pro-
vides a close loop transfer function with the highest zero
crossover frequency and sufficient phase margin.
F
=
ESR
2´ p ´ ESR´ COUT
The FLC is the double-pole frequency of the two-phase LC
filters, and FESR is the frequency of the zero introduced by
the ESR of the output capacitors.
The transfer function of error amplifier is given by :
1
1
æ
ö
÷
ø
// R2 +
ç
VPHASE1
L1=L
L2=L
VOUT
VCOMP
VOUT
sC1
sC2
è
GAINAMP
=
=
1
æ
ö
R1// R3 +
ç
÷
sC3
è
ø
COUT
ESR
VPHASE2
æ
ö
ö
1
1
æ
ç
´ s +
÷
÷
s +
ç
÷
ç
R2´ C2
(
R1+ R3
)
´ C3
R1+ R3
è
ø
è
C1+ C2
ø
=
´
R1´ R3´ C1
æ
ö æ
1
ö
s s +
´ s +
÷ ç
ç
÷
R2´ C1´ C2
R3´ C3
è
ø è
ø
Figure 5. The Output LC Filter
Copyright ã ANPEC Electronics Corp.
21
www.anpec.com.tw
Rev. A.6 - Oct., 2009
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
