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APW7098QAE-TRG 参数 Datasheet PDF下载

APW7098QAE-TRG图片预览
型号: APW7098QAE-TRG
PDF下载: 下载PDF文件 查看货源
内容描述: 两相降压PWM控制器集成MOSFET驱动器 [Two- Phase Buck PWM Controller with Integrated MOSFET Drivers]
分类和应用: 驱动器开关控制器
文件页数/大小: 30 页 / 650 K
品牌: ANPEC [ ANPEC ELECTRONICS COROPRATION ]
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APW7098  
Application Information (Cont.)  
PWM Compensation (Cont.)  
4. Set the pole at the ESR zero frequency FESR  
FP1 = FESR  
:
The pole and zero frequencies of the transfer function  
Calculate the C1 by the following equation:  
are:  
1
FZ1  
FZ2  
=
2´ p ´ R2´ C2  
C2  
C1=  
2´ p ´ R2´ C2´ FESR - 1  
1
=
=
2´ p ´  
(R1+R3  
)
´ C3  
5. Set the second pole FP2 at the half of the switching  
frequency and also set the second zero FZ2 at the output LC  
filter double pole FLC. The compensation gain should not  
exceed the error amplifier open loop gain, check the  
compensation gain at FP2 with the capabilities of the  
error amplifier.  
1
F
P1  
C1´ C2  
æ
ö
÷
ø
2´ p ´ R2´  
ç
C1+ C2  
è
1
F
=
P2  
2´ p ´ R3´ C3  
C1  
FP2 = 0.5 X FSW  
R3  
C3  
R2  
C2  
FZ2 = FLC  
VOUT  
Combine the two equations will get the following  
component calculations:  
FB  
VCOMP  
R1  
R1  
R3 =  
VREF  
FSW  
- 1  
Figure 8. Compensation Network  
2´ F  
LC  
The closed loop gain of the converter can be written as:  
GAINLC X GAINPWM X GAINAMP  
1
C3 =  
p ´ R3´ FSW  
Figure 9. shows the asymptotic plot of the closed loop  
converter gain, and the following guidelines will help to  
design the compensation network. Using the below  
guidelines should give a compensation similar to the  
curve plotted. A stable closed loop has a -20dB/ decade  
slope and a phase margin greater than 45 degree.  
FZ1 FZ2  
FP1  
FP2  
Compensation Gain  
20log  
(R2/R1)  
20log  
(VIN/ΔVOSC  
)
1. Choose a value for R1, usually between 1K and 5K.  
2. Select the desired zero crossover frequency  
FO= (1/5 ~ 1/10) X FSW  
FLC  
Use the following equation to calculate R2:  
FESR  
Converter Gain  
DVOSC FO  
R2 =  
´
´ R1  
PWM & Filter Gain  
V
F
LC  
IN  
Frequency(Hz)  
3. Place the first zero FZ1 before the output LC filter double  
pole frequency FLC.  
Figure 9. Converter Gain and Frequency  
Output Inductor Selection  
FZ1 = 0.75 X FLC  
Calculate the C2 by the equation:  
The duty cycle (D) of a buck converter is the function of  
the input voltage and output voltage. Once an output volt-  
age is fixed, it can be written as:  
1
C2 =  
2´ p ´ R2´ FLC ´ 0.75  
Copyright ã ANPEC Electronics Corp.  
22  
www.anpec.com.tw  
Rev. A.6 - Oct., 2009  
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