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APW7098QAE-TRG 参数 Datasheet PDF下载

APW7098QAE-TRG图片预览
型号: APW7098QAE-TRG
PDF下载: 下载PDF文件 查看货源
内容描述: 两相降压PWM控制器集成MOSFET驱动器 [Two- Phase Buck PWM Controller with Integrated MOSFET Drivers]
分类和应用: 驱动器开关控制器
文件页数/大小: 30 页 / 650 K
品牌: ANPEC [ ANPEC ELECTRONICS COROPRATION ]
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APW7098  
Application Information (Cont.)  
Input Capacitor Selection (Cont.)  
Phigh-side = IOUT 2(1+ TC)(RDS(ON))D + (0.5)( IOUT)(V )( tSW)FSW  
IN  
Plow-side = IOUT 2(1+ TC)(RDS(ON))(1-D)  
RMS current of the bulk input capacitor is roughly calcu-  
lated as the following equation :  
where  
I
is the load current  
IOUT  
OUT  
IRMS =  
´
2D×(1- 2D)  
2
TC is the temperature dependency of RDS(ON)  
FSW is the switching frequency  
For a through hole design, several electrolytic capacitors  
may be needed. For surface mount design, solid tan-  
talum capacitors can be used, but caution must be exer-  
cised with regard to the capacitor surge current rating.  
tSW is the switching interval  
D is the duty cycle  
Note that both MOSFETs have conduction losses while  
the high-side MOSFET includes an additional transi-  
tion loss. The switching interval, tSW, is the function of  
the reverse transfer capacitance CRSS. The (1+TC) term is  
a factor in the temperature dependency of the RDS(ON) and  
can be extracted from the “RDS(ON) vs. Temperature” curve  
of the power MOSFET.  
MOSFETSelection  
The APW7098 requires two N-Channel power MOSFETs  
on each phase. These should be selected based upon  
RDS(ON), gate supply requirements, and thermal manage-  
ment requirements.  
In high-current applications, the MOSFET power  
dissipation, package selection, and heatsink are the domi-  
nant design factors. The power dissipation includes two  
loss components, conduction loss, and switching loss.  
The conduction losses are the largest component of  
power dissipation for both the high-side and the low-  
side MOSFETs. These losses are distributed between  
the two MOSFETs according to duty factor (see the equa-  
tions below). Only the high-side MOSFET has switching  
losses since the low-side MOSFETs body diode or an  
external Schottky rectifier across the lower MOSFET  
clamps the switching node before the synchronous rec-  
tifier turns on. These equations assume linear voltage-  
current transitions and do not adequately model power  
loss due the reverse-recovery of the low-side MOSFET  
body diode. The gate-charge losses are dissipated by  
the APW7098 and don’t heat the MOSFETs. However,  
large gate-charge increases the switching interval, tSW  
which increases the high-side MOSFET switching  
losses. Ensure that all MOSFETs are within their maxi-  
mum junction temperature at high ambient temperature  
by calculating the temperature rise according to package  
thermal-resistance specifications. A separate heatsink  
may be necessary depending upon MOSFET power,  
package type, ambient temperature and air flow.  
Layout Consideration  
In any high switching frequency converter, a correct layout  
is important to ensure proper operation of the regulator.  
With power devices switching at higher frequency, the  
resulting current transient will cause voltage spike across  
the interconnecting impedance and parasitic circuit  
elements. As an example, consider the turn-off transition  
of the PWM MOSFET. Before turn-off condition, the  
MOSFET is carrying the full load current. During turn-off,  
current stops flowing in the MOSFET and is freewheeling  
by the low side MOSFET and parasitic diode. Any parasitic  
inductance of the circuit generates a large voltage spike  
during the switching interval. In general, using short and  
wide printed circuit traces should minimize interconnect-  
ing impedances and the magnitude of voltage spike.  
Besides, signal and power grounds are to be kept sepa-  
rating and finally combined using ground plane construc-  
tion or single point grounding. The best tie-point between  
the signal ground and the power ground is at the nega-  
tive side of the output capacitor on each channel, where  
there is less noise. Noisy traces beneath the IC are not  
recommended. Figure 10. illustrates the layout, with bold  
lines indicating high current paths; these traces must be  
short and wide. Components along the bold lines should  
be placed lose together. Below is a checklist for your  
layout:  
For the high-side and low-side MOSFETs, the losses are  
approximately given by the following equations:  
Copyright ã ANPEC Electronics Corp.  
24  
www.anpec.com.tw  
Rev. A.6 - Oct., 2009  
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