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AS1524-BTDR 参数 Datasheet PDF下载

AS1524-BTDR图片预览
型号: AS1524-BTDR
PDF下载: 下载PDF文件 查看货源
内容描述: 下150ksps , 12位, 1通道伪/真差分和2路单端ADC [150ksps, 12-Bit, 1-Channel Pseudo/True-Differential and 2-Channel Single-Ended ADCs]
分类和应用:
文件页数/大小: 22 页 / 708 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1524/AS1525  
Datasheet - Application Information  
9 Application Information  
Automatic Shutdown Mode  
With CNVST low, the AS1524/AS1525 default to automatic shutdown (< 0.2µA) mode after power-up and between  
conversions. After detecting a rising edge of CNVST, the AS1524/AS1525 powers up, sets DOUT low, and enters  
track mode.  
After detecting a falling edge of CNVST, the device enters hold mode and begins the conversion. A maximum of 3.7µs  
later, the device completes conversion, enters shutdown, and MSB is available at DOUT.  
External Reference  
An external reference is required for the AS1524/AS1525. Use a 4.7µF bypass capacitor for best performance. The  
reference input structure allows a voltage range of +1V to VDD + 50mV.  
Performing a Conversion  
1. Use a general-purpose I/O line on the CPU to hold CNVST low between conversions.  
2. Drive CNVST high to acquire AIN1(AS1525) or unipolar mode (AS1524). To acquire AIN2 (AS1525) or bipolar  
mode (AS1524), drive CNVST low and high again.  
3. Hold CNVST high for 1.4µs.  
4. Drive CNVST low and wait approximately 3.7µs for conversion to complete. After 3.7µs, the MSB is available  
at DOUT.  
5. Activate SCLK for a minimum of 12 rising clock edges. DOUT transitions on SCLK’s falling edge and is avail-  
able in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the µP on  
SCLK’s rising edge.  
Standard Interface Connections  
The AS1524/AS1525 serial interface is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is avail-  
able, establish the processor’s serial interface as a master so that the CPU generates the serial clock for the AS1524/  
AS1525 and select a clock frequency up to 8MHz.  
SPI and Microwire Interface  
When using an SPI (Figure 23) or Microwire interface (Figure 24), set CPOL = CPHA = 0. Two 8-bit readings are nec-  
essary to obtain the entire 12-bit result from the AS1524/AS1525. DOUT data transitions on the serial clock’s falling  
edge and is clocked into the processor on SCLK’s rising edge. The first 8-bit data stream contains the first 8-bits of  
DOUT starting with the MSB. The second 8-bit data stream contains the remaining four result bits. DOUT then goes  
high impedance.  
Figure 23. SPI Serial Interface Connections  
8
SCK  
I/O  
SCLK  
AS1524/  
AS1525  
6
CPU  
SSM  
CNVST  
7
MISO  
DOUT  
www.austriamicrosystems.com  
Revision 1.02  
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