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AS1524-BTDR 参数 Datasheet PDF下载

AS1524-BTDR图片预览
型号: AS1524-BTDR
PDF下载: 下载PDF文件 查看货源
内容描述: 下150ksps , 12位, 1通道伪/真差分和2路单端ADC [150ksps, 12-Bit, 1-Channel Pseudo/True-Differential and 2-Channel Single-Ended ADCs]
分类和应用:
文件页数/大小: 22 页 / 708 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1524/AS1525  
Datasheet - Detailed Description  
Figure 19. Single Conversion – AIN1 vs. GND (AS1525), Unipolar Mode AIN+ vs. AIN- (AS1524)  
Sampling Instant  
tCONV  
tACQ  
CNVST  
SCLK  
DOUT  
1
4
8
12  
High Z  
High Z  
B11  
MSB  
B0  
LSB  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
If AIN2 is selected (see Figure 20), drive CNVST high for at least 30ns. Next, drive CNVST low for at least 30ns, and  
then high again. This powers up the AS1525 and places the track/hold circuitry in track mode with AIN2 connected to  
the positive input capacitor. Next hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the  
track/hold circuitry in hold mode. The AS1525 then performs a conversion and shuts down automatically. The MSB is  
available at DOUT after 3.7µs. Data can then be clocked out using SCLK.  
Note: If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is selected for the next conversion.  
Selecting Unipolar or Bipolar Conversions (AS1524)  
True-differential conversion (with the AS1524 unipolar and bipolar modes) is selected using pin CNVST (see page 3).  
AIN+ and AIN- are sampled at the falling edge of CNVST. In unipolar mode, AIN+ can exceed AIN- by up to VREF. The  
output format is straight binary. In bipolar mode, either input can exceed the other by up to VREF/2. The output format is  
two’s complement. In both modes, the input common mode range can go from GND to VDD.  
Figure 20. Single Conversion – AIN2 vs. GND (AS1525), Bipolar Mode AIN+ vs. AIN- (AS1524)  
Sampling Instant  
tCONV  
tACQ  
CNVST  
SCLK  
DOUT  
1
4
8
12  
High Z  
High Z  
B11  
B0  
LSB  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
MSB  
Note: In unipolar and bipolar modes, AIN+ and AIN- must not exceed VDD by more than 50mV or be lower than GND  
by more than 50mV.  
If unipolar mode is selected (see Figure 19), drive CNVST high to power up the AS1524 and place the track/hold cir-  
cuitry in track mode with AIN+ and AIN- connected to the input capacitors. Hold CNVST high for tACQ to fully acquire  
the signal. Drive CNVST low to place the track/hold circuitry in hold mode. The AS1524 then performs a conversion  
and shutdown automatically. The MSB is available at DOUT after 3.7µs. Data can then be clocked out using SCLK.  
Clock out all 12 bits of data before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out  
before CNVST is driven high, bipolar mode is selected for the next conversion.  
If bipolar mode is selected (see Figure 20), drive CNVST high for at least 30ns. Next, drive CNVST low for at least  
30ns and then high again. This places the track/hold circuitry in track mode with AIN+ and AIN- connected to the input  
capacitors.  
Next hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the track/hold circuitry in hold  
mode. The AS1524 then performs a conversion and shuts down automatically. The MSB is available at DOUT after  
3.7µs. Data can then be clocked out using SCLK.  
Note: If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode is selected for the next con-  
version.  
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