AS1524/AS1525
Datasheet - Application Information
Table 6. SSPCON Register Settings
AS1524/AS1525
Control Bit
Setting
Synchronous Serial Port Control Register (SSPCON)
Write Collision Detection Bit
WCOL
Bit 7
Bit 6
X
X
Receive Overflow Detect Bit
SSPOV
Synchronous Serial Port Enable
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port
pins.
SSPEN
CKP
Bit 5
Bit 4
1
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
0
0
1
SSPM3:1 Bit 3:1
SSPM0 Bit 0
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and
selects FCLK = fOSC / 16.
Table 7. SSPSTAT Register Settings
AS1524/AS1525
Control Bit
Setting
Synchronous Serial Status Register (SSPSTAT)
SPI Data Input Sample Phase. Input data is sampled at the middle of the
data output time.
SMP
CKE
Bit 7
Bit 6
0
1
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the
serial clock.
Data Address Bit
Stop Bit
D/A
P
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
Start Bit
S
Read/Write Bit Information
Update Address
Buffer Full Status Bit
R/W
UA
BF
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