AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.3 SSP – Synchronous Serial Port
The SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals
having one of the following:
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a Motorola SPI-compatible interface
a TI synchronous serial interface
a National Semiconductor MicroWire interface
In both master and slave configurations the SSP performs
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parallel-to-serial conversion on data written to an internal 16-bit wide, 8-location deep transmit FIFO
serial-to-parallel conversion on received data, buffering it in a similar 16-bit wide, 8 location-deep receive FIFO
Interrupts are generated to:
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request servicing of the transmit and receive FIFO
inform the system that a receive FIFO overrun has occurred
inform the system that data is present in the receive FIFO after an idle period has expired
SSP Features:
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compliant to AMBA Rev 2.0
master or slave operation
programmable clock bit rate and prescale
separate receive and transmit memory buffers each 16 bits wide and 8 bits deep
programmable data frame size from 4 to 16 bit
independent masking of receive FIFO, transmit FIFO and receive overrun interrupts
internal loopback testmode available
support for DMA
identification register uniquely identifying the PrimeCell™ itself (support for OS)
SPI features:
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full-duplex, four wire synchronous transfer
programmable clock polarity and phase
MicroWire features:
half duplex transfer using 8 bit control message
Texas Instruments SSI features:
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full-duplex, four wire synchronous transfer
transmit data PIN tristateable when not transmitting
Programmable parameters:
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master or slave mode
enabling of operation
frame format
communication baud rate
clock phase and polarity
data width from 4 to 16 bit
interrupt masking
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