AMS73CAG01808RA
Conditions
Symbol - H7
- I9
Unit
Burst Refresh Current; CKE: High; External clock: On; tCK, CL, nRFC: see timing used table; BL: 8;
AL: 0; CS: High between REF; Command, Address: partially toggling; Data IO: FLOATING; DM:stable
at 0; Bank Activity: REF command every nRFC; Output Buffer and RTT: Enabled in Mode Registers;
ODT Signal: stable at 0
IDD5B
mA
260
10
270
Self Refresh Current: Normal Temperature Range; TCASE: 0- 85°C; Auto Self-Refresh (ASR): Dis-
abled; Self-Refresh Temperature Range (SRT): Normal; CKE: Low; External clock: Off; CK and CK:
LOW; CL: see timing used table; BL: 8; AL: 0; CS, Command, Address, Data IO: FLOATING; DM: sta- IDD6
ble at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers;
ODT Signal: FLOATING
mA
mA
10
18
Self Refresh Current: Extended Temperature Range; TCASE: 0- 95°C; Auto Self-Refresh (ASR):
Disabled; Self-Refresh Temperature Range (SRT): Extended; CKE: Low; External clock: Off; CK and
CK: LOW; CL: see timing used table; BL: 8; AL: 0; CS, Command, Address, Data IO: FLOATING; DM: IDD6ET
stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: En-
abled in Mode Registers; ODT Signal: FLOATING
18
Operating Bank Interleave Read Current; CKE: High; External clock: On; tCK, nRC, nRAS, nRCD,
nRRD, nFAW, CL: see timing used table; BL: 8; AL: CL-1; CS: High between ACT and RDA; Com-
mand, Address: partially toggling; Data IO: read data bursts with different data between one burst and IDD7
the next one; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with
different addressing; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
270
8
310
8
mA
mA
RESET Low Current; RESET: Low; External clock: off; CK and CK: LOW; CKE: FLOATING; CS,
IDD8
Command, Address, Data IO: FLOATING; ODT Signal : FLOATING
NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM
7) Read Burst type : Nibble Sequential, set MR0 A[3]=0B
Timing used for IDD and IDDQ Measured - Loop Patterns
Speed
CL-nRCD-nRP
tCKmin
DDR3-1066
7-7-7 8-8-8
DDR3-1333
8-8-8 9-9-9
Unit
1.875
1.5
ns
CL
7
7
8
8
8
8
9
9
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
tRCDmin
tRCmin
27
28
33
34
tRASmin
tRPmin
20
20
7
8
8
9
tFAW
20
4
20
4
tRRD
tRFC - 1Gb
59
74
AMS73CAG01808RA Rev. 1.0 December 2010
21
AMS [ Advanced Monolithic Systems Ltd ]
