AMS73CAG01808RA
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
Slew Rate [V/ns]
Min.
75
57
50
38
34
29
22
13
0
Max.
Min.
175
170
167
163
162
161
159
155
150
150
Max.
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
0
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain
requirements for single-ended signals.
CK and CK have to approximately reach VSEH min / VSEL max [ approximately equal to the AC-levels
( VIH(AC) / VIL(AC) ) for Address/command signals ] in every half-cycle.
DQS, DQS have to reach VSEH min / VSEL max [ approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ
signals ] in every half-cycle proceeding and following a valid transition.
Note that the applicable AC-levels for Address/command and DQ’s might be different per speed-bin etc.
E.g. if VIH150(AC) / VIL150(AC) is used for Address/command signals, then these AC-levels apply also for
the single-ended components of differential CK and CK.
AMS73CAG01808RA Rev. 1.0 December 2010
17
AMS [ Advanced Monolithic Systems Ltd ]
