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AMS73CAG01408RAUJH7 参数 Datasheet PDF下载

AMS73CAG01408RAUJH7图片预览
型号: AMS73CAG01408RAUJH7
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能的1Gbit DDR3 SDRAM [HIGH PERFORMANCE 1Gbit DDR3 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 31 页 / 683 K
品牌: AMS [ Advanced Monolithic Systems Ltd ]
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AMS73CAG01808RA  
Speed Bin Table Notes  
NOTE :  
1. The CL setting and CWL setting result in tCK(avg) Min and tCK(avg) Max requirements. When making a selection  
of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.  
2. tCK(avg) Min limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL -  
all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC  
standard tCK(avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding  
up to the next "Supported CL".  
3. tCK(avg) Max limits: Calculate tCK(avg) = tAA Max / CL Selected and round the resulting tCK(avg) down to the  
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(avg) Max corresponding to CL  
selected.  
4. "Reserved" settings are not allowed. User must program a different value.  
5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature.  
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are  
not subject to production tests but verified by design/characterization.  
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are  
not subject to production tests but verified by design/characterization.  
8. tREFI depends on operating case temperature (Tc).  
9. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower.  
SPD settings must be programmed to match. For example, DDR3-1333(CL9) devices supporting down binning to  
DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin  
(Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accord-  
ingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9).  
AMS73CAG01808RA Rev. 1.0 December 2010  
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