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AMS73CAG01408RAUJH7 参数 Datasheet PDF下载

AMS73CAG01408RAUJH7图片预览
型号: AMS73CAG01408RAUJH7
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能的1Gbit DDR3 SDRAM [HIGH PERFORMANCE 1Gbit DDR3 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 31 页 / 683 K
品牌: AMS [ Advanced Monolithic Systems Ltd ]
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AMS73CAG01808RA  
AC and DC Logic Input Levels for Differential Signals  
Differential signals definition  
tDVAC  
VIH.DIFF.AC.MIN  
VIH.DIFF.MIN  
0.0  
half cycle  
VIL.DIFF.MAX  
VIL.DIFF.AC.MAX  
tDVAC  
time  
Definition of differential ac-swing and "time above ac level" tDVAC  
Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)  
Differential AC and DC Input Levels  
Symbol  
VIHdiff  
Parameter  
Min.  
+0.2  
Max.  
NOTE 3  
Units  
Notes  
Differential input high  
Differential input low  
Differential input high AC  
Differential input low AC  
V
V
V
V
1
1
2
2
VILdiff  
NOTE 3  
-0.2  
VIHdiff(AC)  
VILdiff(AC)  
2 x (VIH(AC) - VREF)  
NOTE 3  
NOTE 3  
2 x (VREF - VIL(AC))  
NOTE :  
1. Used to define a differential signal slew-rate.  
2. for CK - CK use VIH/VIL(AC) of address/command and VREFCA; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs  
and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.  
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respec-  
tive limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and under-  
shoot. Refer to "Overshoot and Undershoot specification".  
AMS73CAG01808RA Rev. 1.0 December 2010  
16