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AMS73CAG01408RAUJH7 参数 Datasheet PDF下载

AMS73CAG01408RAUJH7图片预览
型号: AMS73CAG01408RAUJH7
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能的1Gbit DDR3 SDRAM [HIGH PERFORMANCE 1Gbit DDR3 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 31 页 / 683 K
品牌: AMS [ Advanced Monolithic Systems Ltd ]
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AMS73CAG01808RA  
VREF Tolerances  
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in  
figure VREF(DC) tolerance and VREF AC-Noise limits. It shows a valid reference voltage VREF(t) as a  
function of time. (VREF stands for VREFCA and VREFDQ likewise).  
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to  
meet the min/max requirement in Table of “Single-Ended AC and DC Input Levels for Command and  
Address”. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD.  
voltage  
VDD  
VSS  
time  
VREF(DC) tolerance and VREF AC-Noise limits  
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are  
dependent on VREF.  
"VREF" shall be understood as VREF(DC), as defined in figure above, VREF(DC) tolerance and VREF AC-  
Noise limits.  
This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid  
high or low level and therefore the time to which setup and hold is measured. System timing and voltage  
budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the  
input signals.  
This also clarifies that the DRAM setup/hold specification and derating values need to include time and volt-  
age associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the speci-  
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.  
AMS73CAG01808RA Rev. 1.0 December 2010  
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