A43E26161
Page Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
*Note 2
CCc
CDd
RAa
RBb
CAa
CBb
RCc
RDd
ADDR
BS1
BS0
A10/AP
RAa
RBb
RCc
RDd
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 CDd2
DQ
t
RDL
t
CDL
WE
*Note 1
DQM
Precharge
(All Banks)
Write
(A-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Write
(C-Bank)
: Don't care
* Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.
(December, 2004, Version 1.0)
27
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
