A43E26161
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4
0
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CLOCK
CKE
CS
RAS
CAS
Ra
Ca
Cc
Cb
ADDR
BS1
BS0
A10/AP
Ra
WE
* Note 1
DQM
DQ
Qa0
Qa1
Qb0
Qb1
Dc0
Dc2
Qa2
Qa3
t
SHZ
tSHZ
Read
Bank 0
Read
Bank 0
Clock
Suspension
Write
DQM
Row Active
Read DQM
Write
Bank 0
Clock
Suspension
: Don't care
* Note : DQM needed to prevent bus contention.
(December, 2004, Version 1.0)
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AMIC Technology, Corp.