A43E26161
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
t
RCD
RAS
CAS
*Note 2
ADDR
BS0
Ra
Ca
Cb
Cc
Cd
BS1
A10/AP
WE
Ra
t
RDL
t
CDL
*Note1
*Note3
DQM
DQ
(CL=2)
Qb2
Qb1
Qa0
Qa1
Qb0
Qb1
Qb0
Dc0
Dc0
Dc1
Dc1
Dd0
Dd0
Dd1
Dd1
DQ
(CL=3)
Qa0
Qa1
Row Active
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
(December, 2004, Version 1.0)
25
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
