A43E26161
Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
*Note 1
RC
t
CS
t
RCD
RAS
CAS
*Note 2
ADDR
Ra
Ca0
Rb
Cb0
BS0
BS1
A10/AP
WE
Ra
Rb
DQM
t
OH
DQ
(CL = 2)
Qa0
Qa1
Qa2
Qa3
Db0
Db0
Db1
Db2
Db3
t
RAC
*Note 4
t
RDL
t
SAC
tSHZ
*Note 3
t
OH
DQ
(CL = 3)
Qa0
Qa1
Qa2
Qa3
Db1
Db2
Db3
t
RAC
*Note 4
t
RDL
t
SHZ
t
SAC
*Note 3
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clock.
3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
(December, 2004, Version 1.0)
24
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
