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A25L080Q4-UFG 参数 Datasheet PDF下载

A25L080Q4-UFG图片预览
型号: A25L080Q4-UFG
PDF下载: 下载PDF文件 查看货源
内容描述: 16Mbit的低电压,串行闪存的100MHz统一4KB扇区 [16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors]
分类和应用: 闪存
文件页数/大小: 43 页 / 681 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L016 Series  
Page Program (PP)  
The Page Program (PP) instruction allows bytes to be  
programmed in the memory (changing bits from 1 to 0).  
Before it can be accepted, a Write Enable (WREN) instruction  
must previously have been executed. After the Write Enable  
(WREN) instruction has been decoded, the device sets the  
Write Enable Latch (WEL).  
programmed correctly within the same page. If less than 256  
Data bytes are sent to device, they are correctly programmed  
at the requested addresses without having any effects on the  
other bytes of the same page.  
S
Chip Select ( ) must be driven High after the eighth bit of the  
last data byte has been latched in, otherwise the Page  
Program (PP) instruction is not executed.  
The Page Program (PP) instruction is entered by driving Chip  
S
Select ( ) Low, followed by the instruction code, three  
S
As soon as Chip Select ( ) is driven High, the self-timed  
address bytes and at least one data byte on Serial Data Input  
(DIO). If the 8 least significant address bits (A7-A0) are not all  
zero, all transmitted data that goes beyond the end of the  
current page are programmed from the start address of the  
same page (from the address whose 8 least significant bits  
Page Program cycle (whose duration is tPP) is initiated. While  
the Page Program cycle is in progress, the Status Register  
may be read to check the value of the Write In Progress (WIP)  
bit. The Write In Progress (WIP) bit is 1 during the self-timed  
Page Program cycle, and is 0 when it is completed. At some  
unspecified time before the cycle is completed, the Write  
Enable Latch (WEL) bit is reset.  
S
(A7-A0) are all zero). Chip Select ( ) must be driven Low for  
the entire duration of the sequence.  
The instruction sequence is shown in Figure 12. If more than  
256 bytes are sent to the device, previously latched data are  
discarded and the last 256 data bytes are guaranteed to be  
A Page Program (PP) instruction applied to a page which is  
protected by the Block Protect (BP2, BP1, BP0) bits (see  
table 1 and table 2) is not executed.  
Figure 12. Page Program (PP) Instruction Sequence  
S
0
1
2
3
4
5
6
7
8
9 10  
28 29 30 31  
33 34 35 36 37 38 39  
Data Byte 1  
32  
7
C
Instruction  
24-Bit Address  
23  
21  
2
1
0
22  
3
5
4
1
0
6
3
2
DIO  
MSB  
MSB  
S
C
40 41 42 43 44 45 46  
Data Byte 2  
48 49 50 51 52 53 54 55  
Data Byte 3  
47  
Data Byte 256  
DIO  
0
5
4
1
5
4
1
6
3
2
0
6
7
3
2
5
4
1
6
3
2
0
7
7
MSB  
MSB  
MSB  
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.  
(March, 2012, Version 2.0)  
19  
AMIC Technology Corp.  
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