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A25L080Q4-UFG 参数 Datasheet PDF下载

A25L080Q4-UFG图片预览
型号: A25L080Q4-UFG
PDF下载: 下载PDF文件 查看货源
内容描述: 16Mbit的低电压,串行闪存的100MHz统一4KB扇区 [16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors]
分类和应用: 闪存
文件页数/大小: 43 页 / 681 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L016 Series  
Block Erase (BE)  
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside  
the chosen block. Before it can be accepted, a Write Enable  
(WREN) instruction must previously have been executed.  
After the Write Enable (WREN) instruction has been decoded,  
the device sets the Write Enable Latch (WEL).  
S
instruction is not executed. As soon as Chip Select ( ) is  
driven High, the self-timed Block Erase cycle (whose duration  
is tBE) is initiated. While the Block Erase cycle is in progress,  
the Status Register may be read to check the value of the  
Write In Progress (WIP) bit. The Write In Progress (WIP) bit  
is 1 during the self-timed Block Erase cycle, and is 0 when it  
is completed. At some unspecified time before the cycle is  
completed, the Write Enable Latch (WEL) bit is reset.  
A Block Erase (BE) instruction applied to a page which is  
protected by the Block Protect (BP2, BP1, BP0) bits (see  
table 1and table 2) is not executed.  
The Block Erase (BE) instruction is entered by driving Chip  
S
Select ( ) Low, followed by the instruction code on Serial  
S
Data Input (DIO). Chip Select ( ) must be driven Low for the  
entire duration of the sequence.  
The instruction sequence is shown in Figure 14. Chip Select  
S
(
) must be driven High after the eighth bit of the instruction  
code has been latched in, otherwise the Block Erase  
Figure 14. Block Erase (BE) Instruction Sequence  
S
6
0
1
2
3
4
5
7
8
9 10  
28 29 30 31  
C
Instruction  
24-Bit Address  
22  
3
23  
21  
2
1
0
DIO  
MSB  
Note:. Address bits A23 to A21 are Don’t Care, for A25L016.  
(March, 2012, Version 2.0)  
21  
AMIC Technology Corp.  
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